Logic circuit having common load element

ABSTRACT

A logic circuit comprises a first logic block composed of one or more metal-insulator-semiconductor field-effect transistors (MISFETs), a second logic block composed of one or more MISFETs, and a transfer gate MISFET adapted to be turned on and off between the first and second logic blocks: Current control MISFETs are connected in series with the respective logic blocks and driven by clock pulses differing in phase so as to prevent the current control elements from coincidentally turning on, and a load MISFET is commonly connected to the first and second logic circuit.

States Patent Unite Nomiya ELEMENT Dec. 9, 1975 [75] Inventor: Kosei Nomiya Tokyo Japan sign Electronics (pub.); pp. 3032, 37-38; 3/1971. [73] Assignee: Hitachi, Ltd., Ja a Low Threshold Voltages Switch MOS Registers;

Electronics (pub.)' 8/21/1967- pp. 147-148. 2 Fl d: [2 1 16 Nov 1973 Lohman, Applications of MOSFETS 1n Microelec- PP 13,322 tronics; SCP and Solid State Technology (pub.);

30 Forei A lication Priorit Data 1 N 6 5 y 47 0319 Primary ExaminerMichael J. Lynch ov. apan Assistant Examiner L' N Anagnos 52 us. ca 307/205; 307/215; 307/221 c; Attorney Anmneu 307/224 C [51] Int. Cl. ..H03K 19/08; H03K 19/34; [57] ABSTRACT 314- 19/22; 1 1 l /20 A logic circuit comprises a first logic block composed Fleld 05 Search 221 of one or more metal-insulator-semiconductor field- /2 C, 269 effect transistors (MISFETs), a second logic block composed of one or more MlSFETs, and a transfer References Clted I gate MISFET adapted to be turned on and off be- UNTTED STATES PATENTS tween the first and second logic blocks: Current con- 3,3e5,707 l/l968 Mayhew 307/205 x MISFETS are connemd in Series with the respec' 3,497,715 2 1970 Yen 307/221 0 X five logic blocks and driven y Clock P11lses differing 3,510,787 5/1970 Pound et at, 307/205 X in phase so as to prevent the current control elements 3,526,783 9/1970 Booher 307/205 from coincidentally turning on, and a load MISFET is ,750 2/1972 Campbe 307/205 X commonly connected to the first and second logic cir- 3,700,9s1 10/1972 Masahura et a]. 307/205 x cum 3,775,693 11/1973 Proebsting 307/218 X 2 Claims, 5 Drawing Figures '-Voo 4 E II QrI If t Qrz Vin QSI V2 Qsz Va Qsa Q54 w -'il:Q1l F012 F013 L 1F014 l 7 01 7 =f=C2 =1- "7" 091 Qgz l-- US. Patent Dec. 9, 1975 Sheet 1 of3 3,925,686

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US. Patent Dec. 9, 1975 Sheet 2 01 3 3,925,686

Y Patent )ec.9, 1975 Sheet 3 of3 3,925,686

FIG. 5

LOGIC CIRCUIT HAVING COMMON LOAD ELEMENT BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical circuit, particularly to a dynamic shift register, which is composed of insulated gate field-effect transistors (hereinbelow termed MISFETs).

2. Description of the Prior Art In general, a logical circuit of the so-called EE type is known in which MISFETs of the enhancement type are used for both the load and driving or inverter MIS- FETs. Further, as one means to lower the power consumption thereof, there is known a clock drive circuit in which the load transistor is driven by clock pulses.

On the other hand, the ED type circuit employing a MISFET of the depletion type as a load transistor can make the supply voltage low. In addition, due to the constant-current characteristic of the depletion type MISFET, the ED type circuit has such excellent properties as low power consumption, and high speed operation. Further, the ED type circuit is more suitably formed into an integrated circuit than the EB type circuit with respect to a high degree of integration. As a fact to be noted of this circuit, whenever a driving transistor is conducting, a current flows through the series circuit including the load and driving transistors.

The present invention has been made in order to obtain a circuit which has the merits of both the foregoing ED type circuit and clock drive circuit. In the ED type circuit, the gate potential of the depletion type MIS- FET serving as the load must be kept constant relative to the source potential thereof. It is, therefore, difficult to drive the load directly by clock pulses.

To fulfill such features of the ED type circuit and the clock drive circuit, a circuit as shown in FIG. has been proposed in US. patent application Ser. No. 381,485, entitled MISFET LOGIC CIRCUIT HAV- ING DEPLETION TYPE LOAD TRANSISTOR, filed July 23, 1973, and assigned to the assignee of the present application.

In the circuit shown in FIG. 5, Q, to QM are depletion type MISFETs used as load transistors. 01, to O1 O to 0, Q and Q are enhancement type MIS- FETs.

Each of the transistors Qrl to Q has its gate electrode connected to its source electrode to obtain a good constant-current characteristic.

In the circuit arrangement in FIG. 5, the enhancement type MISFETs QI,QI are respectively connected to the depletion type load MISFETS Qr -Qr The enhancement type MISFET Qg for current limitation is connected in common with the source electrodes of the MISFETs Q1 and Q1 and has clock pulses applied to its gate electrode. The MISFET Qg is connected in common with the source electrodes of the MISFETs Q1 and Q1 and has applied to its gate electrode clock pulses which differ in phase from the clock pulses (b The MISFETs Or Q1 and Qg constitute an inverter circuit (NOT circuit). Similarly, the other MISFETs constitute three respective inverter circuits. The respective inverter circuits are connected in cascade through transfer gate circuits constructed of the enhancement type MISFETs Qs -Qs An output signal is provided from the inverter circuit at the final stage 2 through the MISFET Qs The clock pulses (in are applied to the gate electrodes of the MISFETs Os and Qs while the clock pulses (b are applied to the gate electrodes of the MISFETs Qs and Qs Applied to the gate electrode of the MISFET Ql are input signals V which are synchronized with the clock pulses 05 With such a construction, in the proposed circuit, the inverter circuits operate only during the periods of time during which the clock pulses are applied. Thus, an ED type MIS circuit which is capable of clock drive operation is realized.

There is a general requirement of increasing the density of circuit elements in an integrated circuit. To this end, a further improvement is necessary in the ED type MIS circuit capable of clock drive operation.

SUMMARY OF THE INVENTION It is an object of this invention to provide a MIS circuit which can be built as a semiconductor integrated circuit with improved circuit element density, low power consumption, and high speed operation.

It is another object of the present invention to provide an ED type MIS circuit which can be clock-driven.

According to one embodiment, a logic circuit according to this invention is characterized by a common load of a depletion type MOSFET commonly connected to a pair of inverter circuits each of which includes a series connection of an inverter MOSFET and a current limiting MOSFET, both of enhancement type. The current limiting transistors are clock-driven by clock pulses to be alternately rendered conductive.

The characterizing features of the present invention will become apparent from the following detailed description taken in conjunction with the. accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of an embodiment of the MISFET logical circuit employin g a depletion type load transistor according to the present invention;

FIG. 2 is a timing diagram for explaining the operation of the shift register in FIG. 1;

FIGS. 3 and 4 are circuit diagrams each showing another embodiment of the present invention; and

FIG. 5 is a circuit diagram of a shift register which has been previously proposed.

PREFERRED EMBODIMENTS OF THE INVENTION FIG. 1 is a circuit diagram of a shift register according to the present invention. Qr and Qr designate MISFETs of the depletion type in which even when the bias voltage between the gate and the source is O V, a fixed current flows between the source and the drain. They are used as load transistors.

On the other hand, Oi -Q1 Qs Qs and Qg as well as Qg are MISFETs of the enhancement type in which when a bias voltage above a certain threshold level is applied between the gate and the source, a current flows between the source and the drain for the first time.

In order to provide a good constant-current characteristic, each of the MISFETs Or, and Qr has its gate electrode connected to its source electrode.

The current-limiting elements (MISFETs) Qg and Qg are respectively connected in series with the first logical blocks (MISFETs Q] with odd reference numerals) Q1 and Q1 and the second logical blocks (MIS- 3 FETs Ql with even reference numerals) Q1 and 01,, the logical blocks satisfying a predetermined logic relationship.

The MISFETs Q1, and Qg, constitute an inverter circuit. Similarly, the other combination of MISFETs Q1, and Q82, Q1 and Q81, and Ql and Q82 Constitute inverter circuits, respectively. The inverter circuits are connected in cascade through the enhancement type MISFETs Qs,Qs for transfer. From the inverter circuit at the final stage, an output signal is derived through the MISFET Qs,. The load transistor Or, is connected in common with the inverter transistors Q1, and Q1 for supplying a potential from a power source V,,,, to the logical blocks. Similarly, the load Qr is connected in common with the inverter transistors Q1 and G1,. The transfer transistor Qs, is connected between the drain of transistor Q1, and the gate of transistor Q1 Similarly, the transistors Qs, and Qs, are connected between transistors Q1 and Q1 and between transistors Q1 and Q1 respectively. The output is derived from the drain of transistor Q1 through transfer transistor Qs,.

A train of clock pulses (b, is applied to the gate electrodes of the current-limiting element Qg, and the transfer elements Qs, and'Qs while a train of clock pulses 115 is applied to the gate electrodes of the current-limiting element Qg, and the transfer elements Qs, and Qs,. The clock pulses (b, and d), differ in phase so as to be prevented from simultaneously turning on all the MISFETs. An input signal V, synchronized with the clock pulse (1), is applied to the gate electrode of the MISFET Q1 The operation of the shift register thus constructed will now be explained with reference to the timing diagram shown in FIG. 2. In the figure, the upper level of each signal indicates a logical 1 (ground potential), while the lower level represents a logical O (a negative potential).

When the clock pulse (b, becomes to render the MISFET Qg, conductive, the output signal of the first inverter circuit or the drain voltage V, of the MISFET Ql, becomes the inverted signal of the input signal V,,,.

Since, at this time, the transfer MISFET Qs, is also conductive, the output signal V, is fed therethrough to the MISFET Q1 and is stored in the gate capacitance C, of the MISFET Q1 Since the circuit of the present invention uses the load in common, the output signal V, from the input signal is delivered as the drain source potential of the MISFET Q1 being the inverter circuit at the succeeding stage. Herein, since the current-limiting MISFET Qg, which is controlled by the clock pulse is not conductive, no current flows therethrough, and the delivery of the output signal V, is not affected by the output of the second logical circuit. Next, the clock pulse 4), becomes 1, the MISFET Qg, turns off", and the inverter circuit at the first stage reverts to the original state. At this time, the charge stored in the gate capacitance C, of the MISFET 01 is retained.

When the clock pulse becomes 0 to turn the MIS- FETs Qg, and Qs on, the inverted signal of the signal stored in the MISFET O1, is written into the gate capacitance C of the MISFET Q1 At this time, for a reason similar to the above, the second stage inverter circuit is not influenced by the first stage.

Thus, because the gate voltage V, of the MISFET O1, is synchronized with the clock pulse 4), and the input signal V,-,, is synchronized with the clock pulse (b the gate potential V, becomes equal to a signal with the input signal V,-,, delayed by a phase difference between the clock pulses d), and Since the periods of the clock pulse series 11 and are equal, the gate potential V, of the MISFET Q1 ultimately becomes equal to a signal with the input signal V,-, delayed by one period (one bit) of the clock pulse series (I), or

FIG. 3 shows another embodiment of the present invention. In the embodiment, the inverter transistor O1, in FIG. 1 is replaced by a multi-input logic block LB, which is constituted by series connected inverter MOS- FETs Ql and 01,, of enhancement type and an inverter MOSFET 01, of enhancement type connected in parallel with the series circuit of transistors Q1 and Ql,,. The transistors Ql to 01,, are supplied with various input signals Va to Vc at their gate electrodes, respectively.

Also, the inverter transistor Q1 is replaced by a multiinput logic block LB, which is constituted by parallelconnected inverter MOSFETs G1 and Q1 of the enhancement type. To the gate of transistor Ql the output of logic block LB, is applied through transfer gate MOSFET Qs,. The MOSFET Q1 is supplied with an appropriate input signal V at its gate.

The circuit of FIG. 3 having the common load MOS- FET of depletion type can be clock-driven by the clock pulses d), and (I), applied to the transistors Qg, and Qg in the same manner as in the circuit of FIG. 1.

Further, gate element MISFETs Qg, and Qg, may also be inserted, as shown in FIG. 4, between a load MISFET Or and logical block MISFETs Q], and Q1 In this case, the same effect in circuitry is obtained.

Although the foregoing embodiments are driven by the two-phase clock pulses 4), and (1),, the present invention can be similarly performed in cases of three or more phases.

Needless to say, the present invention is also applicable to a load which cannot be driven directly by pulses, as in the case of using a mere resistance in place of the load MISFET Qr, or to an enhancement type MISF ET load in the case where the clock drive of the load is impossible due to the layout of elements and wiring in the integration of the circuitry.

Owing to the ED system especially employing the MISFET of the depletion type as the load in the present invention of the foregoing construction, the supply voltage can be made low. Owing to the constant-current characteristic of the depletion type MISFET, the excellent properties of low power consumption, high speed and high degree of integration are attained. Also, owing to the adoption of the clock drive, a decrease in the power consumption is accomplished. Furthermore, the number of load elements is reduced by half.

While I have shown and described several embodiments in accordance with the present invention, it is understood that the same is not limited thereto but is susceptible of numerous changes and modifications as known to a person skilled in the art, and I therefore do not wish to be limited to the details shown and described herein but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the an.

What I claim is:

1. A logic circuit having first and second clock controlled logic stages, each logic stage comprising:

a depletion type load MISFET having a drain electrode connected to a first terminal, a source electrode connected to a second terminal and a gate electrode connected to said second terminal;

a first logic block connected between said second terminal and a third terminal, said first logic block comprising at least one first MISFET having a gate electrode, a drain electrode electrically connected to said second terminal and a source electrode electrically connected to said third terminal;

a second logic block connected between said second terminal and a fourth terminal, said second logic block comprising at least one second MISFET having a gate electrode, a drain electrode electrically connected to said second terminal and a source electrode electrically connected to said fourth terminal;

said depletion load MISFET acting as a common load for the transistors in said first and second logic blocks;

a third MISFET having a gate electrode, a drain electrode connected to said third terminal and a source electrode connected to a ground terminal;

a fourth MISFET having a gate electrode, a drain electrode connected to said fourth terminal and a source electrode connected to the ground terminal;

a fifth MISFET having a gate electrode and two output electrodes, one of said output electrodes being connected to said second terminal and the other 6 output electrode being connected to the gate electrode of said at least one second MISFET in said second logic block;

a sixth MISFET having a gate electrode and two output electrodes, one of the output electrodes being connected to the second terminal;

means for applying an electrical potential to said first terminal;

means for applying a first clock pulse signal simultaneously to the gate electrodes of said third MISF ET and said fifth MISFET;

means for applying a second clock pulse signal simultaneously to the gate electrodes of said fourth MIS- PET and said sixth MISFET, said second clock pulse signal being different from said first clock pulse signal in phase; and

means for applying an input signal to the gate electrode of said first MISFET, wherein said third and fourth MISFETs, respectively, of said first logic stage are the third and fourth MISFETs of said second logic stage.

2. A logic circuit according to claim 1, wherein all of the MISFETs in said first and second logic blocks and said third, fourth, fifth and sixth MISFETs are of enhancement type. 

1. A logic circuit having first and second clock controlled logic stages, each logic stage comprising: a depletion type load MISFET having a drain electrode connected to a first terminal, a source electrode connected to a second terminal and a gate electrode connected to said second terminal; a first logic block connected between said second terminal and a third terminal, said first logic block comprising at least one first MISFET having a gate electrode, a drain electrode electrically connected to said second terminal and a source electrode electrically connected to said third terminal; a second logic block connected between said second terminal and a fourth terminal, said second logic block comprising at least one second MISFET having a gate electrode, a drain electrode electrically connected to said second terminal and a source electrode electrically connected to said fourth terminal; said depletion load MISFET acting as a common load for the transistors in said first and second logic blocks; a third MISFET having a gate electrode, a drain electrode connected to said third terminal and a source electrode connected to a ground terminal; a fourth MISFET having a gate electrode, a drain electrode connected to said fourth terminal and a source electrode connected to the ground terminal; a fifth MISFET having a gate electrode and two output electrodes, one of said output electrodes being connected to said second terminal and the other output electrode being connected to the gate electrode of said at least one second MISFET in said second logic block; a sixth MISFET having a gate electrode and two output electrodes, one of the output electrodes being connected to the second terminal; means for applying an electrical potential to said first terminal; means for applying a first clock pulse signal simultaneously to the gate electrodes of said third MISFET and said fifth MISFET; means for applying a second clock pulse signal simultaneously to the gate electrodes of said fourth MISFET and said sixth MISFET, said second clock pulse signal being different from said first clock pulse signal in phase; and means for applying an input signal to the gate electrode of said first MISFET, wherein said third and fourth MISFETs, respectively, of said first logic stage are the third and fourth MISFETs of said second logic stage.
 2. A logic circuit according to claim 1, wherein all of the MISFETs in said first and second logic blocks and said third, fourth, fifth and sixth MISFETs are of enhancement type. 